| DIGITAL I/O CHANNELS |
| Logic Families |
LVTTL, LVDS, configurable for 1.2 / 2.5 / 3.3 V logic; 5 V compatible, programmable per pin via the FPGA |
| Output Current |
±12.0 mA, max. Programmable per pin via the FPGA |
| Input Leakage Current |
±10 µA |
| Power on State |
Default is disconnected at power on (unprogrammed FPGA) or defined by FPGA program |
| Number of Channels |
32 Differential digital I/O lines
64 Single-ended digital I/O line |
| FIFO Depth |
2047 Samples |
| Maximum FIFO Clock Rate |
10 MHz |
| Clock Sources |
PXI triggers, Ext Trigger, Star X, PXI Clk10, PXI Clk100 (Express version), DSTAR (Express version), Local bus |
| Protection |
Overvoltage: -0.5 V to 7.0 V (input)
Short circuit: up to 8 outputs may be shorted at a time |
| ANALOG INPUT CHANNELS |
| Number of Channels |
8 differential or 16 single-ended |
| Sample Rate |
250 KS/s (simultaneous) or
1 MS/s (two channels) |
| Bus Transfer Modes |
DMA, Interrupt, Register I/O |
| Resolution |
16-bits |
| Accuracy |
± 13.60V Range: ± 7.50mV
± 10.24V Range: ± 6.50mV
± 5.12V Range: ± 4.50mV
± 2.56V Range: ± 4.0mV |
| Input Voltage Ranges (FS VDC) |
± 13.6*
± 10.24
± 5.12
± 2.56
± 1.28
± 0.64
* Uses the gain value for the 20.48 VDC range |
| Input Impedance |
500 M ohms |
| Analog BW (3 dB) |
8 MHz |